1. Field of the Invention
The present invention relates to a three-dimensional (3D) stacked memory array, and more particularly to a 3D stacked memory array enabling to select layers as a general method or to improve the degree of integrity of a memory by selecting layers as many as possible under the limited number of threshold voltage states of string selection transistors and the limited number of string selection lines (SSLs), and to a method for determining threshold voltages of string selection transistors of the same array.
2. Description of the Related Art
Recently, there has been difficulty in improving the degree of integrity under 20 nm due to limitation of the photolithography technology. So, various memory arrays enabling a 3D stack have been studied.
When the memory structure having a 3D stacked shape is compared with the conventional two-dimensional (2D) planar structure, the greatest difference is a necessity of a layer selection in the 3D stacked memory structure during operation.
These days, the various 3D structures enabling a layer selection in the operation of writing (a program) and reading (a read) are being studied. One example is a 3D NAND flash memory array performing a layer selection by electrical erases described in Korean Patent No. 10-1147526.
The prior art is known as a structure performing a layer selection by erase operation (LASER). According to this structure, each SSL (LSL shown in FIG. 1 of Korean Patent No. 10-1147526 is equal to SSL) and a body of an active line separately formed by each layer are used to extract electrons from a specific charge storage layer between the SSL and the body of the active line in each layer for electrically forming an erase state combination, namely an initialized state combination, instead of the impurity-doped layer combination physically formed in the conventional Korean Patent No. 10-1036155. So, it has merits that the layer selection can be more easily performed.
However, because the LASER structure is consisted of sting selection transistors formed at locations crossed between each SSL and an active line (each layer of bit lines) and simply divided into initialized transistors and not, there have been some limitations in improving the degree of integrity by minimizing the number of SSLs for a layer selection.
When n is the number of SSLs and r is the number of initialized string selection transistors formed in each active line, the number of vertically stacked layers to be selected is equal to a combination expressed as nCr. To obtain the maximum value of nCr, r has to be the closest natural number to the middle value of n.
To overcome the limitations of the LASER structure, a method of a layer selection by multi-level operation (LSM) has been suggested in Korean Patent No. 10-1370509. In the LSM method, because the threshold voltages of string selection transistors in adjacent string selection lines are reversely distributed from each other, when the number of threshold voltage states is 4, it is possible that total 2n layer selections can be selected by n as the number of SSLs (if n is an even number and k is the number of threshold voltage states, k(n/2) layers can be selected).
Because the LSM method distributes the threshold voltages of the string selection transistors in a couple of string selection lines, the more the number of SSLs is increased, the more the number of selectable layers is increased. However, if n is an odd number, there has been a problem that one of SSLs is not paired.
By looking for a method for more efficiently selecting layers as many as possible under the limited numbers of threshold voltage states and SSLs than the method for reversely distributing the threshold voltages in a pair of two SSLs, the inventors have finally contrived the present invention.